| 摘要 |
<p>The present invention has an input amplifier circuit (20) that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors (QL1, QL2) that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor. The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET (M3). The current through the second amplifier determines the output signal VOUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors.</p> |
