| 摘要 |
PROBLEM TO BE SOLVED: To provide a means for reducing clock skew while maintaining the phase lock of a clock signal independently of a system mode. SOLUTION: The method includes a step for closing the phase lock loop feedback route of a phase lock loop by a real clock signal outputted from a real clock tree. The real clock tree is selectively stopped, so that a normal operation mode is shifted to a test mode. The phase lock loop feedback route of the phase lock loop is closed by a copy clock signal outputted from a copy clock tree, so that the locked state of the phase lock loop is maintained. A step for stopping the real clock tree and a step for closing the phase lock loop feedback route by the copy clock signal are completed within a single clock cycle so as to maintain the lock during the period of switching from the normal operation mode to the test mode. |
