| 摘要 |
<p>A phase locked loop (PLL) is provided for synchronizing a PLL output signal to a plurality of reference clock signals and for aligning the PLL output signal with a distributed frame signal. The PLL includes a slew controlled frame aligner for controlling the phase deviation in the feedback signal of the PLL to thereby control the phase deviation of the PLL output so as to meet a particular phase deviation timing requirement. The slew controlled frame aligner includes a ramp generator for generating a plurality of digital add and skip pulses that are coupled to the feedback counter in the PLL to thereby control the equivalent analog phase added to or subtracted from the feedback signal.</p> |
