发明名称 Method of addressing a number of peripheral modules by the central unit in a bus system
摘要 The system has a central unit (10) and a number of peripheral modules (20), of which each contains a control circuit (24) and a connected information transmitter/receiver device which is connected to a first and second input/output connection (21,22) of the module. The individual input/output connections are each connected to only one input/output connection of one other module or of the central unit, so that the peripheral module is connected to the central unit either directly or via one or more transmitter/receiver devices to exchange data with it.
申请公布号 EP0807887(A3) 申请公布日期 2002.01.30
申请号 EP19970107341 申请日期 1997.05.03
申请人 CONTI TEMIC MICROELECTRONIC GMBH 发明人 FENDT, GUENTER
分类号 B60R16/02;B60R16/03;B60R21/01;G05B9/02 主分类号 B60R16/02
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