| 摘要 |
PURPOSE: To provide a DLL (Delay Locked Loop) circuit that provides an output of a clock signal of one system fixed with respect to both leading and trailing edges of a clock signal with a decreased chip size and reduced power consump tion. CONSTITUTION: A 1st phase decision circuit 1 and a 2nd phase decision circuit 2 receive an internal clock outputted from a pulse width variable circuit 4, the 1st phase decision circuit 1 decides a phase relation between an external clock D1 and the internal clock D3 to provide an output of a 1st phase decision signal D4, and the 2nd phase decision circuit 2 decides a phase relation between the external clock D1 and the internal clock D3 to provide an output of a 2nd phase decision signal D5. An optional phase generating circuit 3 adjusts a phase a reference clock D2 on the basis of the 1st phase decision signal D4 to output an adjusted reference clock D2' to the pulse width variable circuit 4, and the pulse width variable circuit 4 adjusts the pulse width of the adjusted reference clock D2' on the basis of the 2nd phase decision signal D3. |
