| 摘要 |
PURPOSE: An address detection test mode circuit is provided to know a short type fail of a cell gap node easily by generating a test mode flag before a normal test and entering a redundancy test mode if a specific address is inputted while testing a normal cell and again performing the normal mode test if the redundancy region goes by. CONSTITUTION: The circuit includes a flag generation part(10) generating a test mode flag to perform entry and exit of a test mode, and a register part(20) outputting a control signal per constant period according to a flag signal generated in the flag generation part and a row access input indicating a redundancy operation. A counter part(30) outputs bit data corresponding to the number of main word lines existing in one mat according to a control signal applied from the register part. And a decoding part(40) outputs a redundant main word line active signal by decoding the bit data applied from the counter part.
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