| 摘要 |
PROBLEM TO BE SOLVED: To improve the data transfer efficiency of a data bus. SOLUTION: This system is provided with a continuous data transfer number setting register 4 for setting the amount of data, which can be continuously transferred when a DMAC 1 acquires a bus use right, a temporary request stopping means 5 for stopping transmitting the bus use right requesting signal of the DMAC 1 to a competition control part 6 equal to or longer than one clock period without fail after the end of set data transfer and a DMA priority setting register 7 for performing an arbitration so that the bus use right can be next applied to the DMAC 1 without fail when the bus use right requesting signal of the DMAC 1 is generated in the competition control part 6. Thus, the bus use right is assigned to the DMAC 1 and a CPU and i/f 8.
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