| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay circuit the delay time of which can be adjusted, even after the completion of the circuit formation and the delay time of which can accurately be measured. SOLUTION: The delay circuit is provided with logic gates 101-110, each having two input terminals and that are connected in cascade, an operating power supply means (consisting of MOSFETs QN3, QN4,..., QN7, QN8) that supplies the same operating power to the logic gates 101-110 and an operating power supply revision means 145 that changes the operating power supply voltage, depending on a control voltage. The logic gates 101-110 adopt the same CMOS circuit configuration, and the logic gates 101-110 are connected in cascade in such a way that the output signal of a pre-stage logic gate (101-109) is given to one of the input terminals of a 2nd and succeeding stage of the logic gate (102-110) and a prescribed signal is given to the other input terminal and the same load capacitance is connected to an output of each logic gate.</p> |
