| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an inverter circuit, having much delay that can reduce the circuit area and the manufacturing cost. SOLUTION: The inverter circuit 10 includes a PMOS 11P and an NMOS 11N that delays an input signal IN, a PMOS 12P that gives a signal which is delayed by the PMOS 11P to a gate terminal to arise an output signal OUT, and an NMOS 12N that receives the signal delayed by the NMOS 11N to a gate terminal, to decrease the output signal. The PMOS 11P and the NMOS 11N can delay the output signal the input signal more than that by the conventional inverter circuit. Since the number of delay circuits in the inverter circuit can be reduced, the circuit area can be decreased, and the manufacturing cost can be reduced.</p> |
