| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency division clock communication method where deterioration in clock waveform can be reduced and to provide a communication apparatus there a limit of device selection attended with the propriety of a PLL mounted on the unit is relaxed, a timing design including dispersion in a chopper circuit due to power supply/temperature fluctuations is facilitated and employing inexpensive devices with low power consumption can reduce the cost of the communication unit. SOLUTION: The communication method of this invention is characterized in that a clock signal is frequency-divided, a 1st frequency division clock signal frequency-divided from the clock signal is transmitted, the clock signal is inverted and then frequency-divided, a 2nd frequency division clock signal having a phase difference of 90-degrees from the phase of the 1st frequency division clock signal is transmitted, the 1st frequency division clock signal and the 2nd frequency division clock signal are received, and they are multiplied to generate a clock signal identical to the original clock signal. |
