| 摘要 |
PROBLEM TO BE SOLVED: To provide a video signal processor which automatically adjusts the phase of A/D conversion. SOLUTION: A phase controller 9 successively varies the value of a phase control signal pc from 0 to (N-1) during one period of a vertical synchronization signal Vsync and outputs the value to a PLL4. Every time the value of the signal pc increases, the PLL4 shifts the phase of a sampling clock ck for one pixel time divided by N. Thus, the controller 9 computes a horizontal effective video region from the difference between a horizontal video completion position signal HE and a horizontal video starting position signal HS for every value of the signal pc, extracts a horizontal effective video region value that is equal to the number of actual horizontal effective pixels within the given N horizontal effective video region values and determines an optimum phase control signal value among the values of the signals pc corresponding to the extracted horizontal effective video region values (for example, a middle value is determined as an optimum phase control signal value).
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