发明名称 CLOCK SIGNAL GENERATING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a clock signal generating circuit that can regulate fluctuations in biphase clock signals for a non-overlap period caused by dispersion in products. SOLUTION: In the clock signal generating circuit that generates biphase clock signals with a non-overlap period, a NAND gate circuit is provided with a 1st switching element NB, that charges up a capacitor C0 and with a 2nd switching element NA that discharges the capacitor, and controls the 1st and 2nd switching elements NA, NB, depending on the logic of a received clock signal for adjusting the non-overlap period through the charging/discharging of the capacitor C0.</p>
申请公布号 JP2002026703(A) 申请公布日期 2002.01.25
申请号 JP20000207155 申请日期 2000.07.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 NITTA YASUHIKO
分类号 G06F1/06;H03K5/15;(IPC1-7):H03K5/15 主分类号 G06F1/06
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