发明名称 Circuit for eliminating idle cycles in a memory device
摘要 A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.
申请公布号 US2002009014(A1) 申请公布日期 2002.01.24
申请号 US20010804010 申请日期 2001.03.12
申请人 PAWLOWSKI J. THOMAS 发明人 PAWLOWSKI J. THOMAS
分类号 G11C7/10;G11C11/413;(IPC1-7):G11C8/00 主分类号 G11C7/10
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