发明名称 |
Method and device for testing set-up time and hold time of signals of a circuit with clocked data transfer |
摘要 |
For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF-nDELTAt/2; tF+nDELTAt/2]. The fixed delay tF is at least nDELTAt/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.
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申请公布号 |
US2002008503(A1) |
申请公布日期 |
2002.01.24 |
申请号 |
US20010909390 |
申请日期 |
2001.07.19 |
申请人 |
BUCKSCH THORSTEN;SCHNEIDER RALF |
发明人 |
BUCKSCH THORSTEN;SCHNEIDER RALF |
分类号 |
G11C29/02;G11C29/50;(IPC1-7):G01R23/175 |
主分类号 |
G11C29/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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