发明名称 |
METHOD AND DEVICE FOR LOCAL CLOCK GENERATION USING UNIVERSAL SERIAL BUS DOWNSTREAM RECEIVED SIGNALS DP AND DM |
摘要 |
<p>A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters (312, 310, 305, 301) are used to determine a number of periods of a free-running high frequency clock signal ((164) contained within in a known number of bit periods of the downstream received bit-serial signal (146). The counter values are divided by the known number of bit periods of the received bit-signal (146) to determine a bit period of the received bit-serial signal (146). The local clock signal (172) may be phase-locked with the received bit serial signal (146). The local clock period is updated on an ongoing manner by downstream known received traffic.</p> |
申请公布号 |
WO0206935(A1) |
申请公布日期 |
2002.01.24 |
申请号 |
WO2001US22020 |
申请日期 |
2001.07.13 |
申请人 |
SCHLUMBERGER MALCO, INC.;STMICROELECTRONICS, INC. |
发明人 |
LEYDIER, ROBERT, A.;POMET, ALAIN, C. |
分类号 |
G06F1/04;G06K7/00;G06K19/07;H04L7/033;H04L7/04;H04L7/10;(IPC1-7):G06F1/04;G06F1/12 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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