A variable function information processor wherein a logical module (10) constituting the variable function information processor comprises a less number of transistors, the variable function information processor has a function of realizing a combinational logic circuit for conducting full addition of the input signals in accordance with a predetermined control signal and outputting the sum and a sequential circuit for temporarily holding the input signal to delay the signal and output it by only the same logical module, and the number of semiconductor circuit elements constituting the combinational logic circuit and the sequential circuit is decreased further by using the common part of the combinational logic circuit and the sequential circuit for both the circuits, whereby the resources of the variable function information processor can be effectively exploited.
