发明名称 MANUFACTURING METHOD OF MULTI-LAYERED CIRCUIT SUBSTRATE FOR ELECTRONIC COMPONENT
摘要 PROBLEM TO BE SOLVED: To provide a manufacturing method of a multi-layered circuit substrate for electronic components in which the variance of the electrolytic copper plating thickness is reduced to prevent degradation of the performance of the electric signal transmission, the variance of the film thickness of an insulating resin layer is reduced to prevent degradation of the performance as the multi- layered circuit substrate for electronic components. SOLUTION: In this manufacturing method of the multi-layered circuit substrate 11 for electronic components for forming wiring patterns 14, 19 and 22 of each layer by arranging first and second anode electrodes 31 and 32 on both sides of a core substrate 12 having parts to be plated with different areas to achieve the electrolytic copper plating, a first auxiliary cathode electrode 33 separate from the core substrate 12 is arranged on the part to be plated with smaller area of the core substrate 12 to mitigate the variance of the plating thickness on the front and back sides of the core substrate 12.
申请公布号 JP2002020897(A) 申请公布日期 2002.01.23
申请号 JP20000204044 申请日期 2000.07.05
申请人 SUMITOMO METAL ELECTRONICS DEVICES INC 发明人 TOMABECHI SHIGENAO
分类号 C25D7/00;C25D17/10;H01L23/12;H05K3/18;H05K3/46;(IPC1-7):C25D17/10 主分类号 C25D7/00
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