| 摘要 |
To downsize the circuit scale of CPU (2) in a microcomputer capable of executing multiple interrupt, an interrupt controller (4) includes an interrupt mask level register (46). The CPU (2) temporarily transfers or stacks processing data into RAM (6). The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU (2). At the same time, CPU (2) sends a stack signal "STK" to the interrupt controller (4). In response to the stack signal "STK", the interrupt controller (4) temporarily transfers the interrupt mask level stored in the register (46) into RAM (6). When CPU (2) restarts the suspended interrupt processing, CPU (2) reads the PSR value and the PC value from RAM (6) while CPU (2) produces a return signal "RTN." In response to the return signal "RTN", the interrupt mask level is returned from RAM (6) to the register (46). <IMAGE> |
