发明名称 |
Defect analysis method and process control method |
摘要 |
A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.
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申请公布号 |
US6341241(B1) |
申请公布日期 |
2002.01.22 |
申请号 |
US19980206150 |
申请日期 |
1998.12.07 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MUGIBAYASHI TOSHIAKI;HATTORI NOBUYOSHI |
分类号 |
G01N21/88;G01N21/93;G01N21/956;H01L21/66;(IPC1-7):G06F19/00 |
主分类号 |
G01N21/88 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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