| 摘要 |
A clock control system in a network switching node including an internal reference clock of a low level Stratum and receiving a plurality of high level Stratum clocks (CLOCK 1, CLOCK 2, CLOCK n) from connection lines, one of these high level Stratum clocks being currently used to generate a Master Clock; the device selecting another high level Stratum clock when the clock currently used to generate the Master Clock fails and comprising for each high level Stratum clock, means (12, 16, 20) for phase locking the reference clock on the selected high level Stratum clock and obtaining a plurality of phase locked (PLL) reference clocks (SOURCE 1, SOURCE 2, SOURCE n). Phase alignment means (24, 26, 28) are associated with each PLL reference clock for continuously aligning its phase on the phase of the Master Clock if this PLL reference clock is not the one currently used to generate the Master Clock, whereby the Master Clock keeps on being generated without loss of data when the clock currently used to generate the Master Clock happens to fail.
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