| 摘要 |
A CMOS SRAM cell provided with PFET devices as passgate transistors is described to reduce the surface area taken by the pull-up and pull-down devices. A six-transistor, single-port SRAM cell is shown to dissipate 75% less power when compared to conventional cells, and its cell stability improved by a factor of 2. The power saving is the result of the differential sensing made possible with the PFET passgate devices, the smaller standby off-current of the smaller devices and the smaller loading of the short bit lines. The overall SRAM cell is significantly smaller than conventional cells in view that all the six transistors take minimum dimensions. The cell stability is also improved by having the current leakage margin increased to 40mu from a conventional cell current of 10 mua. In another aspect of the invention, an eight-transistor, dual-port cell, the more balanced proportion of 4 PFETs and 4 NFETs in the cell allows a surface area saving of 50% over a conventional layout of 2 PFETs and 6 NFETs. Power saving and stability improvements are also achieved by the PFET port.
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