| 摘要 |
An assembler/disassembler mechanism in a data transfer pipeline receives data from FIFOs on a write operation to a memory, and transfers data to FIFOs on a read operation from memory. An enhanced parity mechanism is implemented in the assembler/disassembler to generate a pseudo-random number for each data byte. Enhanced parity generated in another pipeline component and accompanying data transferred from the FIFO (on a write to memory) is exclusive-ORed with LFSR data generated by enhanced parity circuitry in the assembler/disassembler. Integral registers provide a pathway for a respective line processor to access the data string, and allow the processor to access the memory. A counter mechanism counts/controls the amount of data read into and out of the FIFOs. Setting the amount of data to be transferred in and out of the FIFOs, allows data transfer to effectively run independent of the line processor.
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