发明名称 |
METHOD AND CIRCUIT FOR ACCELERATING REDUNDANT ADDRESS MATCHING |
摘要 |
There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit comprises a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further comprises a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.
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申请公布号 |
WO0205093(A1) |
申请公布日期 |
2002.01.17 |
申请号 |
WO2000CA01409 |
申请日期 |
2000.11.30 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED;DEMONE, PAUL |
发明人 |
DEMONE, PAUL |
分类号 |
G11C7/00;G11C29/00;H03K3/037;(IPC1-7):G06F11/20 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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