Generation of set of test sequences for testing integrated circuit by setting values of non-specified bit positions using systematic filling method

摘要

The method involves defining a list of errors for the integrated circuit, and generating at least one test sequence that defines values for each input signal necessary to detect a target error selected from the list of errors. The values comprise only one section of bits from the test sequence, the remainder being non-specified bit positions. The values of a number of the non-specified bit positions are set using a systematic filling method. An Independent claim is included for an apparatus for generating a set of test sequences.