| 摘要 |
PURPOSE: To provide an ECL(emitter-coupled logic) circuit that attains a high operating speed, high circuit integration and low power consumption. CONSTITUTION: A master latch circuit 1 and a slave latch circuit 2 are configured with the ECL circuits. A drive use ECL circuit 5 receives clock signals CK, XCK to drive the master latch circuit 1 and the slave latch circuit 2. The common drive ECL circuit 5 drives the master latch circuit 1 and the slave latch circuit 2.
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