Multi-chip semiconducting arrangement has module with individual chips' parallel resistance and diode circuits commonly connected to module's gate and clamp connection

摘要

The arrangement has a number of semiconducting chips (Ch1-Chn) connected in parallel in a module with control connections connected in common via a resistance (RG1-RGn) to an external drive circuit (T) on one side and via a diode (D1-D2) to a clamp device (K) on the other side. The module has a gate and clamp connection (G), each resistance and diode within each chip are connected in parallel and the parallel circuits of resistances and diodes of the individual chips are commonly connected to the gate and clamp connection. The arrangement has a number of semiconducting chips (Ch1-Chn) connected in parallel in a module with control connections connected in common via a resistance (RG1-RGn) to an external drive circuit (T) on one side and via a diode (D1-D2) to a clamp device (K) on the other side. The module has a gate and clamp connection (G), each resistance and diode within each chip are connected in parallel and the parallel circuits of resistances and diodes of the individual chips are commonly connected to the gate and clamp connection.