| 摘要 |
PURPOSE: A method for manufacturing a vertical transistor using a standard semiconductor process is provided to manufacture a high-integrated dynamic random access memory(DRAM) device and a high-performance complementary metal-oxide-semiconductor(CMOS) field-effect-transistor(FET), by forming the vertical transistor on a double layer silicon wafer. CONSTITUTION: After a part of an upper silicon layer is etched by a photolithography method, an ion implantation process is performed to form a source/drain region(4). The upper silicon layer is removed to separate devices by a photolithography method. An interlayer dielectric(5) is formed, and is planarized by a chemical mechanical polishing(CMP) method. The planarized interlayer dielectric is dry- or wet-etched to be left by a predetermined thickness from an interface between the upper silicon layer and a buried oxide layer(2). A gate oxide layer(6) and a gate material(7) are consecutively formed, and the gate material is planarized by a CMP method. A predetermined thickness of the gate material is wet- or dry-etched, and an interlayer dielectric(8) is formed. The gate material and the interlayer dielectric are etched by a photolithography method. The interlayer dielectric is etched to form a source/drain region(9) by a photolithography method. Doped polycrystalline silicon is formed by an ion implantation method or epitaxial growth method. The source/drain region is formed by a photolithography method.
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