发明名称 FREQUENCY SYNTHESIZER
摘要 Frequency synthesizer including a phase accumulator (200), a most significant bit selector (250) and a jitter adjusting circuit (260). The most significant bit selector passes the most significant bit of the output of the phase accumulator to a jitter adjusting circuit to remove jitter before outputting a square wave. The jitter adjusting circuit may be, for example, a phase locked loop or a bandpass filter.
申请公布号 WO0205431(A1) 申请公布日期 2002.01.17
申请号 WO2001US12379 申请日期 2001.04.17
申请人 CIENA CORPORATION 发明人 CHIANG, TING-KUANG
分类号 G06F1/025;H03L7/18;(IPC1-7):H03L7/18 主分类号 G06F1/025
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