发明名称 |
Method for making interconnections in an integrated circuit |
摘要 |
<p>A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).</p> |
申请公布号 |
EP1146550(A3) |
申请公布日期 |
2002.01.16 |
申请号 |
EP20010400287 |
申请日期 |
2001.02.06 |
申请人 |
STMICROELECTRONICS S.A.;KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
KORDIC, SRDJAN;TORRES, JOAQUIN;MOTTE, PASCALE;DESCOUTS, BRIGITTE |
分类号 |
H01L23/52;H01L21/3205;H01L23/522;H01L23/532;(IPC1-7):H01L21/285 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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