发明名称 |
MEMORY CIRCUIT, AND SYNCHRONOUS DETECTION CIRCUIT |
摘要 |
The memory circuit of the present invention temporarily stores information symbols included in a reception signal according to a CDMA system which allows multi-code communication to carry out coherent detection using a pilot symbol. The memory circuit of the present invention is constructed of a plurality of electrically independent memory blocks. Each memory block corresponds to one code and one slot of an information symbol. Write access and read access to memory blocks are generated periodically on condition that write access and read access to one memory block do not occur simultaneously. Blocks to which no access is generated are forcibly set to a low power consumption mode to reduce power consumption caused by accesses. <IMAGE> |
申请公布号 |
EP1172957(A1) |
申请公布日期 |
2002.01.16 |
申请号 |
EP20010949075 |
申请日期 |
2001.02.01 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
ARIMURA, TAKUYA |
分类号 |
G06F12/06;G11C5/00;G11C7/10;G11C7/22;G11C8/12;G11C11/41;G11C19/00;H04B1/707;H04B1/7073 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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