| 摘要 |
A method, and associated apparatus, for eliminating pulse width variations in digital delay lines. The method includes partitioning the delay line into two substantially identical blocks of delay inverters and inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated, and the parasitic loading of the inverter between the blocks and the inverter on the output of the second block is the same. Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks.
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