发明名称 A METHOD FOR ALIGNING WAFERS IN A CASSETTE
摘要 A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which bas a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting slots and wafer support means engaging the periphery of each wafer in an individual slot with the central axis of all wafers in coaxial alignment. A supporting platform is placed over the cassette for supporting the wafers in an inverted position in which the wafers are substantially vertical and biased by their own weight against a multiplicity of orienting mechanisms. The orienting mechanisms are arranged to correspond to each wafer position within the cassette. The plurality of orienting mechanisms are intergrated with the supporting platform so that all wafers within the cassette can be aligned during this aligning process. Each orienting mechanism includes a v-block that is mounted substantially normal to and in vertical alignment below each wafer axis, and has two degrees of vertical freedom relative to the supporting platform with springs for biasing the apex of the v-block towards the peripheral edge of the wafer. The v-block is positioned between a pair of supporting friction drive rollers. The rollers are in a first position for engaging the periphery of the wafer and with a mechanism for rotatively driving each roller to impart rotation to the wafer, thereby, with time, aligning the notch to the v-block thus permitting the apex to be urged into the aligned notch. Because the rollers are connected by an assembly to the v-block, they move downwards, away from the wafer, when the v-block moves upwards, and the wafer, now in alignment, ceases to rotate.
申请公布号 SG85650(A1) 申请公布日期 2002.01.15
申请号 SG19990002985 申请日期 1999.06.21
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD 发明人 VIJAI SINHA
分类号 B65G49/07;H01L21/673;H01L21/68;(IPC1-7):B65G49/07 主分类号 B65G49/07
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