发明名称 |
Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof |
摘要 |
A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.
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申请公布号 |
US6339555(B1) |
申请公布日期 |
2002.01.15 |
申请号 |
US20010759358 |
申请日期 |
2001.01.16 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HAMADA MITSUHIRO;YASUDA KENICHI |
分类号 |
G01R31/28;G06F12/16;G11C11/401;G11C11/407;G11C29/12;G11C29/48;G11C29/56;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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