| 摘要 |
A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.
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