| 摘要 |
In order to integrate two FIFOs such as a transmitting FIFO and a receiving FIFO into one FIFO so that a memory area is effectively used, a FIFO memory device 10 comprises a transmitting FIFO control section 20 for writing transmission input data to a memory 100 and outputting the transmitted data written to the memory 100 in order of the data inputting, a receiving FIFO control section 30 for writing receipt input data to the memory 100 and outputting the received data written to the memory 100 in order of the data inputting, a first pointer register 26 for storing the write address of the transmitted data or the read address of the transmission input data in the memory 100, and a second pointer register 36 for storing the write address of the receipt input data or the read address of the receipt output data in the memory 100.
|
