| 摘要 |
PURPOSE: A method for fabricating a CMOS device having a dual titanium polycide gate is provided to prevent a line width effect and an abnormal oxidation phenomenon of a titanium silicide. CONSTITUTION: A field oxide layer(22) is formed on a silicon substrate(21). A P-well(23a) and an N-well(23b) are formed within the silicon substrate(21). A gate oxide layer(24) is grown on the silicon substrate(21). A polysilicon layer(25) is formed on the gate oxide layer(24) and the field oxide layer(22). An n+ polysilicon layer(25a) and a p+ polysilicon layer(25b) are formed on a P-well(23a) and an N-well(23b), respectively. A polysilicon gate is formed on the P-well(23a) and the N-well(23b), respectively. A screen oxide layer is formed on the whole surface of the silicon substrate(21). An LDD(Lightly Doped Drain) region is formed within the wells(23a,23b). A spacer oxide layer is deposited thereon. A spacer(33) is formed on both sidewall of the polysilicon gates. A source/drain region(34) is formed within the wells(23a,23b). An interlayer dielectric(35) is deposited on the whole surface of the above structure. A titanium silicide layer is formed thereon. A crystalline titanium silicide layer(36a) is formed by crystallizing the titanium silicide layer. A mask pattern(37) is formed by depositing and patterning a hard mask thereon. A CMOS device having a dual titanium polycide gate(40a,40b) is completed by etching the crystalline titanium silicide layer(36a).
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