| 摘要 |
A memory system includes an array of memory cells, a controller, a node for receiving a programming voltage, and a voltage detection circuit including first and second voltage divider circuits. The first divider circuit includes first and second impedances in series to form a first node. The second voltage divider circuit includes third and fourth impedances in series. The detection circuit further includes a comparator circuit with an input coupled to the first node and switching circuitry to selectively couple and decouple a junction formed by the third and fourth impedances to the first node. Control circuitry, operably coupled to an output of the comparator circuit, enables the controller to initiate a programming operation when the programming voltage exceeds a first level and the switching circuitry couples the junction to the first node, and causes an initiated programming operation to terminate when the programming voltage drops below a second level and the switching circuitry decouples the junction from the first node.
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