发明名称 |
DESIGN METHOD OF SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR CIRCUIT DESIGNED BY MEANS OF THE SAME |
摘要 |
PROBLEM TO BE SOLVED: To provide the design method of a semiconductor circuit easy in regulating a skew between clock trees and the semiconductor circuit designed by means of it. SOLUTION: After a net list is prepared S1, a plurality of delay gates are previously inserted S1' on the net list, and deleted S7 while the delay gate is regulated so as to satisfy the restriction of timing between clock trees.
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申请公布号 |
JP2002009155(A) |
申请公布日期 |
2002.01.11 |
申请号 |
JP20000184817 |
申请日期 |
2000.06.20 |
申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
FURUMOTO MITSUAKI;NAKAO HIROOMI |
分类号 |
G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/82 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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