| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic module capable of relieving wiring between a plurality of FPGAs by preparatory wiring and achieving yield improvement. SOLUTION: The preparatory wiring 7 of the same net constitution as plural net wiring connected to FPGA on the logic module is provided, when a defect net exists on a plurality of net wirings 5, 6, a library defining the preparatory wiring 7 in place of the defect net as the connection net is possessed, a desired logic is logically divided into plural FPGAs on the logic module, and the arrangement wiring of FPGA is performed to relieve the wiring between FPGAs.
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