发明名称 LOGIC VERIFICATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a logic verification system which automatically repeats a test of logic until the test becomes sufficient by generating a feedback loop for automatically generating test conditions and test data from the result of test sufficiency evaluation obtained by analyzing the coverage of a test conduction result although conventional technology has the problem that the quality of logic verification depends upon the skill of a person in charge since the person evaluates test sufficiency and generates test conditions and test data. SOLUTION: The test of the logic is conducted while the test conditions are automatically generated until the test of the logic becomes sufficient by forming the feedback loop which compares the gate test coverage of the logic simulation test conduction result with test sufficiency evaluation data and automatically generates the test data according to the comparison result.
申请公布号 JP2002007509(A) 申请公布日期 2002.01.11
申请号 JP20000192675 申请日期 2000.06.22
申请人 HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD 发明人 ISHII NOBUSHIGE
分类号 G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/28
代理机构 代理人
主权项
地址