| 摘要 |
<p>PROBLEM TO BE SOLVED: To generate a clock stably which is output outside LSI. SOLUTION: A clock generating circuit for an inside logic synchronizes with (CLK) of PLL1 by inputting (RST) and outputs (CTR) from a clock counter circuit 2. (CLK30), (CLK20), and (CLK60) are generated from each decoder circuit 3, 4, and 5, and they are separated to necessary clock systems and controlled by (CTRL) in a clock control circuit 6. (CLK30A), (CLK30B), (CLK20A), (CLK20B), and (CLK60I) from the clock control circuit 6 are input to an inside logic block 8. The clock generating circuit for outputting outside synchronizes with (CLK) of PLL1 by inputting (RST) and counts up, and a counter circuit for outside clock 10 which outputs (OCTR) and a double frequency divider decoder circuit 11 for outside clock which generates (CLK60O) from (OCTR) are set in an output terminal cell for outside clock 9 separately from the other circuits. The generated outside output clock gets an output of stable frequency without a time lag of starting up.</p> |
