| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit in which a data propagation time on a data line is equalized, a cycle time is shortened, and an internal timing margin is increased. SOLUTION: A memory cell array 1 is constituted by arranging memory cells MC at intersection parts of plural bit, lines BL, /BL and plural word lines WL. The memory cell array 1 is divided into groups A, B, C in the direction of the bit lines BL, /BL, and cell size in the group A being remote from a sense amplifier circuit 4 is set large, cell size in the group C being near the sense amplifier 4 is set small, and cell size in the group B being intermediate is set to an intermediate cell size between the groups A and B. |
