CLOCK RECOVERY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To detect a phase error at every symbol and to secure high speed follow-up performance of clock recovery in the clock recovery circuit of DTV by using a VSB modulation system. SOLUTION: First BPF 8a and second BPF 8b take out the band signal of fs/2 including a pilot signal from the in-phase component and the orthogonal component of a VSB signal converted into a base band. First LPF 9a and second LPF 9b take out the pilot signal. A complex divider 10 complex-divides the outputs of BPF 8a and 8b with the outputs of LPF 9a and 9b. Third BPF 11a and fourth BPF 11b extract the signal of fs/2 from a division result. A complex multiplier 12 squares the signal of fs/2 and converts it into the signal of fs. A phase error detector 14 detects the phase error between the symbol clock of reception VSB and the reference clock of a receiver.