| 摘要 |
PROBLEM TO BE SOLVED: To reduce the mismatch of the threshold voltage Vt of a plurality of MOS type field effect transistors (MOSFET) formed in a semiconductor board and contrive the area reduction. SOLUTION: After an element separation area 2 is formed on a silicon board 1, a P well layer 3 is formed, after ion injection for threshold voltage Vth regulation is performed thereon, mixture gas or the like containing disilane is made a raw material, and epitaxial growth of the silicon layer 6 of low impurity concentration of impurity concentration 1E14 [}cm-3] less is selectively performed. Furthermore, a gate oxide film 7 is formed thereon, after a polysilicon layer 8 is formed, a gate electrode 9 is patterned. Since impurity concentration in an area from 20 >nm] depth to 100 [nm] from an interface between the gate oxide film 7 and the silicon board 1 being the cause of the unevenness of threshold voltage is lowered, the unevenness of the threshold voltage is suppressed.
|
