| 摘要 |
Integrated circuit ferroelectric memory devices are manufactured by forming a first patterned conductive layer on an integrated circuit substrate, to define a lower capacitor electrode and a gate electrode that is spaced apart therefrom. A source region and a drain region are formed on opposite sides of the gate electrode. A ferroelectric layer is formed on the lower capacitor electrode. An upper capacitor electrode is formed on the ferroelectric layer opposite the lower capacitor electrode, to thereby form a ferroelectric capacitor. After forming the upper capacitor electrode, an interconnect layer is formed that electrically connects the top electrode and the source region. A bit line is formed that electrically contacts the drain region. Preferably, both the interconnect layer and the bit line are formed from the same conductive layer. Integrated circuit ferroelectric memory devices include an integrated circuit substrate including an elongated active region therein, and a pair of spaced apart word lines that cross the elongated active region. A drain region is provided in the elongated active region between the pair of word lines. A pair of source regions is provided in the elongated active region, a respective one of which is outside the pair of spaced apart word lines on opposite sides of the drain region. A pair of ferroelectric capacitors are provided outside the elongated active region. A respective one of the ferroelectric capacitors is adjacent a respective one of the pair of source regions. An interconnect layer electrically connects a respective one of the upper capacitor electrodes to a respective one of the source regions and a bit line, electrically connected to the drain region and extending along the integrated circuit substrate orthogonal to the word lines.
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