发明名称 METHOD FOR MANUFACTURING BITLINE USING DUAL DAMASCENE PROCESS
摘要 PURPOSE: A method for manufacturing a bitline using a dual damascene process is provided to basically prevent a lifting phenomenon of a bitline interconnection caused by planarization of a bitline insulation layer, by using the dual damascene process to form a bitline contact and the bitline interconnection. CONSTITUTION: After the first insulation layer is formed on a wordline, an insulation layer for preventing a loss of the first insulation layer and the second insulation layer for the bitline are sequentially formed in a subsequent dual damascene etching process. The second insulation layer, the nitride layer for preventing the loss of the insulation layer and the first insulation layer are etched to form a contact hole for the bitline wherein an impurity adhesion layer(32) is exposed, by using a dual damascene mask. A sidewall nitride layer is formed on the resultant structure, and is blank-etched to form a spacer in contact with the inner wall of the second insulation layer. After a diffusion barrier layer and an interconnection layer for the bitline are sequentially formed on the resultant structure, the interconnection layer for the bitline is blank-etched to be recessed to the inside of the contact hole by a predetermined depth. After a nitride layer for protecting the interconnection layer is formed on the recessed interconnection layer, the nitride layer for protecting the interconnection layer is chemically and mechanically polished to expose the second insulation layer and to form the bitline.
申请公布号 KR20020002528(A) 申请公布日期 2002.01.10
申请号 KR20000036730 申请日期 2000.06.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 OH, CHAN GWON
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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