| 摘要 |
PURPOSE: A wafer level stack package is provided to increase memory density by realizing a stack of at least two semiconductor chips at a wafer level. CONSTITUTION: The first chip(10) has a depressed portion centrally formed in a surface thereof and a bond pad(12) arranged on the bottom of the depressed portion. An insulating layer(20) is formed on the surface of the first chip(10) from the bottom edge of the depressed portion through a sidewall of the depressed portion to a peripheral edge of the chip(10), and a metal pattern(30) is deposited on the insulating layer(20). The metal pattern(30) on the bottom edge of the depressed portion is electrically connected to the bond pad(12) of the first chip(10) via a metal wire(50). The second chip(13) is attached to the bottom of the depressed portion and has such a size as not to protrude from the depressed portion. The depressed portion is filled with encapsulant(60). The second chip(13) has a bond pad arranged on an outer surface thereof and a conductive bump(71) formed on the bond pad thereof. The bump(71) of the second chip(13) and the metal pattern(30) of the first chip(10) are commonly connected to a solder ball(70).
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