Semiconductor memory having double data rate transfer technique

摘要

The semiconductor memory includes a memory cell which handles a clock signal, an address fetch and a command circuit. The memory cell is designated by an address signal and stores data. The clock signal is supplied thereto so as to provide timing for an access to the memory cell, and the clock signal has a leading edge and a trailing edge. The address fetch circuit fetches the address signal for designating the memory cell in synchronism with both of the leading edge and trailing edge of the clock signal. The command circuit fetches a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.