| 摘要 |
Structures and methods are provided for programmable decode circuits which utilize non volatile depletion mode, p-channel floating gate driver transistors. The driver transistors of the present invention have ultra thin gate oxides. The decode circuits of the present invention will work with voltages around one Volt. The decode circuits of the present invention can be programmed with voltages in the range 2.0 to 3.0 Volts. This allows the fabrication of low voltage programmable memory address decode circuits which operate with low voltage power supplies which will be used with CMOS technology which has feature sizes of the order 0.1 mum, 1000 Å, or 100 nm. The address decoder structure includes a number of address lines and a number of output lines which form an array. A number logic cells are disposed at the intersections of output lines and address lines. Further, a number of depletion mode p-channel memory cells are disposed at the intersections of the address lines and at least one output line. The depletion mode p-channel memory cells have a control gate and a floating gate separated from the control gate by a dielectric layer. According to the teachings of the present invention an oxide layer of less than 50 Angstroms (Å) separates the floating gate from a p-type doped channel region between a source and a drain region in the substrate. According to the teachings of the present invention the floating gate is adapted to hold a fixed charge over a limited range of floating gate potentials or electron energies.
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