A NOVEL CAPACITIVELY COUPLED DTMOS ON SOI

摘要

A transistor structure (50) is provided comprising a source region (82, 86) having a N<+> drain region (80) and a N' lightly doped drain region (80) and a N' lightly doped drain region (84). AP<++> heavily doped (110) is provided. The P<++> region (110) resides alongside at least a portion of at least one of the N<-> lightly doped source region (86) and N<-> lightly doped drain region (84). AP<+> body region (120, 158) resides below a gate (90, 156) of the device (50) and between the source (82, 86) and drain (80, 84) regions. The P<++> heavily doped region (110) provides a capacitive coupling between a body region (120, 158) and the gate (90, 156) of the device (50) and form a capacitive voltage divider with the junction capacitance of the device (50).